各引脚的功能为:1引脚:VCC2为主电源引脚。8引脚:VCC1备用电源引脚。备注:DS1302由Vcc1或Vcc2两者中的较大者供电。当Vc的英语翻译

各引脚的功能为:1引脚:VCC2为主电源引脚。8引脚:VCC1备用电源

各引脚的功能为:1引脚:VCC2为主电源引脚。8引脚:VCC1备用电源引脚。备注:DS1302由Vcc1或Vcc2两者中的较大者供电。当Vcc2大于Vcc1+0.2V时,Vcc2给DS1302供电。当Vcc2小于Vcc1时,DS1302由Vcc1供电。由于本设计未引用备用电源,只引用了1引脚,主电源引脚。2和3引脚:X1、X2外接晶振引脚。(外接32.768kHz晶振)4引脚:GND为接地引脚。5引脚:CE/RST为复位/片选线。通过把RST输入驱动置高电平来启动所有的数据传送。1.RST接通控制逻辑,允许地址/命令序列送入移位寄存器;2.RST提供终止单字节或多字节数据的传送手段。6引脚:I/O为数据输入输出口。在控制指令字输入后的下一个SCLK时钟的上升沿时,数据被写入DS1302,数据输入从低位即位0开始。同样,在紧跟8位的控制指令字后的下一个SCLK脉冲的下降沿读出DS1302的数据,读出数据时从低位0位到高位7。7引脚:SCLK为串行时钟,输入。
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源语言: -
目标语言: -
结果 (英语) 1: [复制]
复制成功!
The functions of each pin are: <br>1 pin: VCC2 is the main power pin. <br>8 pins: VCC1 standby power pin. <br>Remark: DS1302 is powered by the greater of Vcc1 or Vcc2. When Vcc2 is greater than Vcc1 + 0.2V, Vcc2 supplies power to DS1302. When Vcc2 is less than Vcc1, DS1302 is powered by Vcc1. Because this design does not refer to the backup power supply, only the 1 pin, the main power pin, is referenced. <br>2 and 3 pins: X1 and X2 are connected to external crystal pins. (External 32.768kHz crystal oscillator) <br>4 pins: GND is the ground pin. <br>5 pins: CE / RST is reset / chip select line. Start all data transfer by driving the RST input high. <br>1. RST turns on the control logic, allowing the address / command sequence to be sent to the shift register; <br>2. RST provides a means of terminating the transmission of single-byte or multi-byte data. <br>6 pins: I / O is the data input and output port. At the next rising edge of the SCLK clock after the control instruction word is input, data is written to the DS1302, and data input starts from the low bit, which is bit 0. Similarly, the DS1302 data is read at the falling edge of the next SCLK pulse immediately following the 8-bit control instruction word, from the low bit 0 to the high bit 7 when reading the data. <br>7 pin: SCLK is the serial clock, input.
正在翻译中..
结果 (英语) 2:[复制]
复制成功!
The functions of each pin are:<br>1 pin: VCC2 is the primary power pin.<br>8 pin: VCC1 backup power pin.<br>Note: The DS1302 is powered by the larger of both Vcc1 or Vcc2. Vcc2 supplies power to the DS1302 when the Vcc2 is greater than Vcc1 plus 0.2V. When Vcc2 is less than Vcc1, the DS1302 is powered by Vcc1. Since the design does not reference the backup power supply, only the 1 pin, the mainpower pin.<br>2 and 3 pins: X1, X2 external crystal pin. (External 32.768kHz crystal)<br>4-pin: GND is ground pin.<br>5-pin: CE/RST is reset/chip selection. All data transferises are initiated by high the RST input drive.<br>1. RST turn-on control logic, allowing the address/command sequence to feed into the shift register;<br>2.RST provides a means of terminating the transmission of single or multi-byte data.<br>6-pin: I/O is the data input port. When the rising edge of the next SCLK clock after the instruction word input is controlled, the data is written to DS1302, and the data input starts at the low position 0. Similarly, the downward severity of the next SCLK pulse, following the 8-bit control instruction, reads the DS1302 data from low 0 to high 7.<br>7-pin: SCLK is serial clock, input.
正在翻译中..
结果 (英语) 3:[复制]
复制成功!
The functions of each pin are:<br>1 pin: VCC2 is the main power pin.<br>8 pin: VCC1 standby power supply pin.<br>Note: DS1302 is powered by the larger of VCC1 or VCC2. When VCC2 is greater than VCC1 + 0.2V, VCC2 supplies power to DS1302. When VCC2 is less than VCC1, DS1302 is powered by VCC1. Because the design does not reference the standby power supply, only 1 pin, the main power supply pin.<br>2 and 3 pins: X1 and X2 are external crystal oscillator pins. (external 32.768KHz crystal oscillator)<br>4 pin: GND is the ground pin.<br>5 pin: CE / RST is reset / chip selection. Start all data transmission by setting RST input driver to high level.<br>1. RST turns on the control logic and allows the address / command sequence to be sent to the shift register;<br>2. RST provides a means to terminate the transmission of single byte or multi byte data.<br>Pin 6: I / O is data input and output port. When controlling the rising edge of the next SCLK clock after the instruction word input, the data is written to DS1302, and the data input starts from the low bit 0. Similarly, the data of DS1302 is read out at the falling edge of the next SCLK pulse immediately following the 8-bit control instruction word, and the data is read out from low bit 0 to high bit 7.<br>7 pin: SCLK is serial clock, input.
正在翻译中..
 
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